DATA SHEET
KH563
recognize that [taking V positive]
Equivalent Model
i
Given that the physical feedback and gain setting
resistors have been determined in accordance with the
design equations shown above, an equivalent model may
be created for the gain to the load where the
amplifier block is taken as a standard op amp. Figure 5
shows this analysis model and the resulting gain
equation to the load.
−
V = V + Gi
R
f
o
err
−
solving for V from two directions
−
V
= V − i R = G +1 i
R
(
)
i
err
i
err g
solving for i from this
err
V
i
i
=
err
G +1 R +R
(
)
g
i
Vi
+
Ro
then
Classical
op-amp
Vo
V R
−
i
i
RL
-
V
= V −
i
G +1 R +R
(
)
g
i
Rf - Ro
−
and, substituting for V and i in the original V expression
err
o
Rg
GR −R
f
i
V = V 1+
o
i
G +1 R +R
(
)
g
i
V
R −R
R
R
R
o
f
o
L
f
= 1+
pulling an
out of the fraction
V
R
R +R
i
g
L
o
g
R
R
i
substitutingin for R andR with their design
equation yields
G −
f
g
V
R
R
o
f
f
A ≡
= 1+
v
R
V
i
i
g
G +1+
V
R
o
L
R
g
= A
= A (gain to load)
L
v
V
R +R
L o
i
R
R
G
G +1
f
note that A = 1+
Figure 5: Equivalent Model
v
g
This model is used to generate the DC error and noise
performance equations. As with any equivalent model,
the primary intent is to match the external terminal
characteristics recognizing that the model distorts the
internal currents and voltages. In this case, the model
would incorrectly predict the output pin voltage swing for
a given swing at the load. But it does provide a simplified
means of getting to the external terminal characteristics.
R = 0
i
Figure 4: Voltage Gain Derivation
Note again that if R = 0 this expression would simplify
i
considerably. Also, if G were very large the voltage gain
expression would reduce to the familiar non-inverting op
amp gain equation. These two performance equations,
shown below, provide a means to derive the design equa-
tions for R and R given a desired no load gain and out-
External Compensation Capacitor (C )
f
g
x
put impedance.
As shown in the test circuit of Figure 1, the KH563 requires
an external compensation capacitor from the output to
pin 19. The recommended values described here assume
that a maximally flat frequency response into a matched
Performance Equations
Design Equations
load is desired. The required C varies widely with
x
R
R
the desired value of output impedance and to a lesser
degree on the desired gain. Note from Figure 2, the
simplified internal schematic, that the actual total
compensation (C ) is the series combination of C and
f
R +R 1+
R = G +1 R − A R
(
)
f
i
f
o
v
i
g
R −R
R =
f
o
o
R
R =
i
g
G +1+
A −1
t
x
v
R
g
the internal 10pF from pin 19 to the compensation nodes.
The total compensation (C ) is developed in two steps as
shown below.
t
R
i
G −
R
R
R
f
f
A = 1+
v
R
R
i
g
300
2.0
G +1+
C =
1−
pF intermediate equation
pF total compensation
1
g
R
R
o
g
C
1
C =
t
1+ 0.02 C
(
)
1
8
REV. 1A January 2008
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
