DATA SHEET
KH205
where:
s
s
s
s
IP3
o
= third-order output intercept, dBm at
the load.
P
o
= output power level, dBm at the load.
HD3
rd
= third-order distortion from the
fundamental, -dBc.
dBm is the power in mW, at the load,
expressed in dB.
high frequency performance. Follow the steps below as
a basis for high frequency layout:
s
s
s
s
Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3
rd
order
distortion are:
s
s
s
s
short and equal return paths from the load
to the supplies.
de-coupling capacitors of the correct value.
higher load resistance.
a lower ratio of the output swing to the
power supply voltage.
s
s
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75
inches of the power pins.
Place the 0.1µF capacitors less than 0.1
inches from the power pins.
Remove the ground plane under and
around the part, especially near the input
and output pins to reduce parasitic
capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins
for prototyping, never use high profile DIP
sockets.
Printed Circuit Layout
As with any high frequency device, a good PCB layout
will enhance the performance of the KH205. Good
ground plane construction and power supply bypassing
close to the package are critical to achieving full perfor-
mance. In the non-inverting configuration, the amplifier is
sensitive to stray capacitance to ground at the inverting
input. Hence, the inverting node connections should be
small with minimal stray capacitance to the ground plane
or other nodes. Shunt capacitance across the feedback
resistor should not be used to compensate for this effect.
General layout and supply bypassing play major roles in
Evaluation PC boards (part number 730008 for inverting,
730009 for non-inverting) for the KH205 are available to
aid in device testing.
6
REV. 1A January 2004
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
