Data Sheet
3
Input
+
-
R
f
R
g
R
s
C
L
R
L
2.5
G=5
Output
Input/Output Voltage (V)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
2
4
6
8
10
12
14
16
18
20
Input
Output
C
omlinear
CLC1011, CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
Figure 6. Addition of R
S
for Driving Capacitive Loads
Table 1 provides the recommended R
S
for various capacitive
loads. The recommended R
S
values result in approximately
<1dB peaking in the frequency response. The Frequency
Response vs. C
L
plot, on page 6, illustrates the response
of the CLCx011.
C
L
(pF)
10pF
20pF
50pF
100pF
R
S
(Ω)
0
0
0
100
-3dB BW (kHz)
2.2
2.4
2.5
2
Time (us)
Figure 7. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
Table 1: Recommended R
S
vs. C
L
For a given load capacitance, adjust R
S
to optimize the
tradeoff between settling time and bandwidth. In general,
reducing R
S
will increase bandwidth at the expense of
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx011 will typically recover in less
than 50ns from an overdrive condition. Figure 7 shows the
CLC1011 in an overdriven condition.
▪
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
▪
Place the 6.8µF capacitor within 0.75 inches of the power pin
▪
Place the 0.1µF capacitor within 0.1 inches of the power pin
▪
Remove the ground plane under and around the part,
▪
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
especially near the input and output pins to reduce
parasitic capacitance
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board
#
CEB011
CEB002
CEB006
CEB010
CEB018
CEB017
Products
CLC1011 in SC70
CLC1011 in SOT23
CLC2011 in SOIC
CLC2011 in MSOP
CLC4011 in SOIC
CLC4011 in TSSOP
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
11
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
