Advance Data Sheet
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 8-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V
S
pin of the amplifier is not
directly connected to the ground plane.
C
omlinear
CLC1011, CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
Figure 7. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa
has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board
#
CEB011
CEB002
CEB006
CEB010
CEB018
CEB017
Products
CLC1011 in SC70
CLC1011 in SOT23
CLC2011 in SOIC
CLC2011 in MSOP
CLC4011 in SOIC
CLC4011 in TSSOP
Figure 8. CEB002 Schematic
Rev 0.0.1
Figure 9. CEB002 Top View
©2009 CADEKA Microcircuits LLC
www.cadeka.com
11
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
