Data Sheet
Application Information
Basic Operation
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+V
s
6.8μF
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 2k ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
perature, the package thermal resistance value Theta
JA
(Ө
JA
) is used along with the total die power dissipation.
T
Junction
= T
Ambient
+ (Ө
JA
× P
D
)
Where T
Ambient
is the temperature of the working environment.
In order to determine P
D
, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
P
D
= P
supply
- P
load
Supply power is calculated by the standard power equa-
tion.
Output
0.1μF
6.8μF
-V
s
R
L
R
f
G = - (R
f
/R
g
)
For optimum input offset
voltage set R
1
= R
f
|| R
g
C
omlinear
CLC2057
Dual, Low Noise, Operational Amplifier
Input
+
-
0.1μF
Output
0.1μF
R
L
R
f
G = 1 + (R
f
/R
g
)
R
g
-V
s
6.8μF
Figure 1. Typical Non-Inverting Gain Circuit
+V
s
6.8μF
R
1
Input
R
g
+
-
0.1μF
P
supply
= V
supply
× I
RMS supply
V
supply
= V
S+
- V
S-
Power delivered to a purely resistive load is:
P
load
= ((V
LOAD
)
RMS
2
)/Rload
eff
The effective load resistor (Rload
eff
) will need to include
the effect of the feedback network. For instance,
Rload
eff
in figure 3 would be calculated as:
Rev 1A
Figure 2. Typical Inverting Gain Circuit
+V
s
6.8μF
R
L
|| (R
f
+ R
g
)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purpos-
es however, prior knowledge of actual signal levels and
load impedance is needed to determine the dissipated
power. Here, P
D
can be found from
Input
+
-
0.1μF
Output
R
L
0.1μF
6.8μF
-V
s
G=1
P
D
= P
Quiescent
+ P
Dynamic
- P
Load
Quiescent power can be derived from the specified I
S
val-
ues along with known supply voltage, V
Supply
. Load power
Figure 3. Unity Gain Circuit
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
9
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
