Data Sheet
can be calculated as above with the desired signal ampli-
tudes using:
(V
LOAD
)
RMS
= V
PEAK
/ √2
( I
LOAD
)
RMS
= ( V
LOAD
)
RMS
/ Rload
eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
DYNAMIC
= (V
S+
- V
LOAD
)
RMS
× ( I
LOAD
)
RMS
Assuming the load is referenced in the middle of the pow-
er rails or V
supply
/2.
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
2
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC2058 will typically recover in less
than 30ns from an overdrive condition. Figure 6 shows the
CLC2058 in an overdriven condition.
C
omlinear
CLC2058
Dual 4V to 36V Amplifier
10
V
IN
= 7.5V
pp
G=5
5
Input
20
10
Output Voltage (V)
Maximum Power Dissipation (W)
Input Voltage (V)
1.5
0
Output
0
1
-5
-10
SOIC-8
-10
0
10
20
30
40
50
-20
0.5
Time (us)
0
-40
-20
0
20
40
60
80
Rev 1C
Ambient Temperature (°C)
Figure 6. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Figure 4. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency re-
sponse, and possible unstable behavior. Use a series re-
sistance, R
S
, between the amplifier and the load to help
improve stability and settling performance. Refer to Fig-
ure 5.
Input
+
-
R
f
R
g
R
s
C
L
R
L
Output
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Figure 5. Addition of R
S
for Driving
Capacitive Loads
Refer to the evaluation board layouts below for more in-
formation.
©2008-2010 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
