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CLC1605 参数 Datasheet PDF下载

CLC1605图片预览
型号: CLC1605
PDF下载: 下载PDF文件 查看货源
内容描述: 单路和三路, 1.5GHz的放大器 [Single and Triple, 1.5GHz Amplifiers]
分类和应用: 放大器
文件页数/大小: 20 页 / 2564 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Driving Capacitive Loads  
In general, avoid adding any additional parasitic capaci-  
tance at this node. In addition, stray capacitance across  
Increased phase delay at the output due to capacitive load-  
ing can cause ringing, peaking in the frequency response,  
and possible unstable behavior. Use a series resistance,  
the R resistor can induce peaking and high frequency  
f
ringing. Refer to the lꢂyꢀꢊꢅ cꢀꢆꢈꢇdꢄꢃꢂꢅꢇꢀꢆꢈ section for  
additional information regarding high speed layout tech-  
niques.  
R , between the amplifier and the load to help improve  
S
stability and settling performance. Refer to Figure 6.  
Overdrive Recovery  
An overdrive condition is defined as the point when either  
one of the inputs or the output exceed their specified volt-  
age range. Overdrive recovery is the time needed for the  
amplifier to return to its normal or linear operating point.  
The recovery time varies, based on whether the input or  
output is overdriven and by how much the range is ex-  
ceeded. The CLC1605 Family will typically recover in less  
than 10ns from an overdrive condition. Figure 7 shows the  
CLC1605 in an overdriven condition.  
Input  
+
-
Rs  
Output  
CL  
RL  
Rf  
Rg  
Figure 6. Addition of R for Driving  
S
Capacitive Loads  
Table 2 provides the recommended R for various capaci-  
S
tive loads. The recommended R values result in <=0.5dB  
peaking in the frequency response. The Frequency Re-  
S
1.5  
1
6
VIN = 2Vpp  
G = 5  
4
sponse vs. C plot, on page 5, illustrates the response of  
L
the CLC1605 Family.  
Input  
0.5  
0
2
Output  
C (pF)  
R (Ω)  
-3dB BW (MHz)  
L
S
0
20  
50  
20  
15  
10  
5
350  
235  
170  
75  
-0.5  
-1  
-2  
-4  
-6  
100  
500  
1000  
-1.5  
3.3  
52  
0
20  
40  
60  
80 100 120 140 160 180 200  
T im e ( n s )  
Figure 7. Overdrive Recovery  
Power Dissipation  
Table 1: Recommended R vs. C  
S
L
For a given load capacitance, adjust R to optimize the  
S
tradeoff between settling time and bandwidth. In general,  
Power dissipation should not be a factor when operating  
under the stated 1000 ohm load condition. However, ap-  
plications with low impedance, DC coupled loads should  
be analyzed to ensure that maximum allowed junction  
temperature is not exceeded. Guidelines listed below can  
be used to verify that the particular application will not  
cause the device to operate beyond it’s intended operat-  
ing range.  
reducing R will increase bandwidth at the expense of ad-  
S
ditional overshoot and ringing.  
Parasitic Capacitance on the Inverting Input  
Physical connections between components create unin-  
tentional or parasitic resistive, capacitive, and inductive  
elements.  
Parasitic capacitance at the inverting input can be espe-  
cially troublesome with high frequency amplifiers. A para-  
sitic capacitance on this node will be in parallel with the  
Maximum power levels are set by the absolute maximum  
junction rating of 150°C. To calculate the junction tem-  
perature, the package thermal resistance value Theta  
JA  
gain setting resistor R . At high frequencies, its imped-  
g
(Ө ) is used along with the total die power dissipation.  
JA  
ance can begin to raise the system gain by making R  
appear smaller.  
g
T
= T + (Ө × P )  
Ambient JA D  
Junction  
©2007-2008 CADEKA Microcircuits LLC  
www.cadeka.com  
16  
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