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CLC1008IST5X 参数 Datasheet PDF下载

CLC1008IST5X图片预览
型号: CLC1008IST5X
PDF下载: 下载PDF文件 查看货源
内容描述: 0.5毫安,低成本, 2.5至5.5V , 75MHz的轨到轨放大器 [0.5mA, Low Cost, 2.5 to 5.5V, 75MHz Rail-to-Rail Amplifiers]
分类和应用: 放大器
文件页数/大小: 17 页 / 3434 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Application Information  
+Vs  
6.8uF  
0.1uF  
General Description  
The CLC1008 family are a single supply, general purpose,  
voltage-feedback amplifiers fabricated on a complementary  
bipolar process. The CLC1008 offers 75MHz unity gain  
bandwidth, 50V/μs slew rate, and only 505μA supply current.  
It features a rail-to-rail output stage and is unity gain stable.  
Input  
+
Output  
-
RL  
0.1uF  
6.8uF  
Figures 1, 2, and 3 illustrate typical circuit configurations for  
non-inverting, inverting, and unity gain topologies for dual  
supply applications. They show the recommended bypass  
capacitor values and overall closed loop gain equations.  
Figure 4 shows the typical non-inverting gain circuit for  
single supply applicaitons.  
G = 1  
-Vs  
Figure 3. Unity Gain Circuit  
+Vs  
The common mode input range extends to 300mV below  
ground in single supply operation. Exceeding these values  
will not cause phase reversal. However, if the input voltage  
exceeds the rails by more than 0.5V, the input ESD devices  
will begin to conduct.  
6.8μF  
+
0.1μF  
In  
+
-
Out  
Rf  
The design uses a Darlington output stage. The output  
stage is short circuit protected and offers “soft” saturation  
protection that improves recovery time.  
Rg  
+Vs  
6.8μF  
Figure 4. Single Supply Non-Inverting Gain Circuit  
0.1μF  
Input  
+
-
Output  
For optimum response at a gain of +2, a feedback resistor  
of 1kΩ is recommended. Figure 5 illustrates the CLC1008  
frequency response with both 1kΩ and 2kΩ feedback  
resistors.  
RL  
0.1μF  
6.8μF  
Rf  
Rg  
G = 1 + (Rf/Rg)  
-Vs  
G = 2  
R = 1kΩ  
R = 2kΩ  
f
Figure 1. Typical Non-Inverting Gain Circuit  
L
+Vs  
R = 1kΩ  
f
6.8μF  
R1  
0.1μF  
+
Output  
Rg  
Input  
-
RL  
0.1μF  
6.8μF  
Rf  
0.1  
1
10  
100  
G = - (Rf/Rg)  
Frequency (MHz)  
-Vs  
For optimum input offset  
voltage set R1 = Rf || Rg  
Figure 5. Frequency Response vs. R  
f
Figure 2. Typical Inverting Gain Circuit  
©2009-2011 CADEKA Microcircuits LLC  
www.cadeka.com  
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