Data Sheet
2.5
reducing R
S
will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
SOIC-8
Maximum Power Dissipation (W)
2
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1006 will typically recover in less
than 25ns from an overdrive condition. Figure 5 shows the
CLC1006 in an overdriven condition.
3
5
4
3
Input
2
1
0
-1
-2
Output
0
-1
-2
-3
-4
-3
0
20
40
60
80
100
120
140
160
180
200
-5
1.5
C
omlinear
CLC1006
Single, 500MHz Voltage Feedback Amplifier
1
0.5
SOT23-5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 3. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
R
S
, between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 4.
Input
+
-
R
f
R
g
R
s
C
L
R
L
V
IN
= 2.5V
pp
G=5
2
1
Output Voltage (V)
Output
Input Voltage (V)
Time (ns)
Figure 5. Overdrive Recovery
Figure 4. Addition of R
S
for Driving
Capacitive Loads
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. CaDeKa
has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
www.cadeka.com
Table 1 provides the recommended R
S
for various capaci-
tive loads. The recommended R
S
values result in <=1dB
peaking in the frequency response. The Frequency Re-
sponse vs. C
L
plots, on page 7, illustrates the response of
the CLC1006.
C
L
(pF)
20
50
100
500
1000
R
S
(Ω)
20
15
11
6
3.3
-3dB BW (MHz)
300
210
150
68
55
Rev 1B
Table 1: Recommended R
S
vs. C
L
For a given load capacitance, adjust R
S
to optimize the
tradeoff between settling time and bandwidth. In general,
©2007-2008 CADEKA Microcircuits LLC
13
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
