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CLC1003ISO8X 参数 Datasheet PDF下载

CLC1003ISO8X图片预览
型号: CLC1003ISO8X
PDF下载: 下载PDF文件 查看货源
内容描述: 低失真,低失调, RRIO放大器 [Low Distortion, Low Offset, RRIO Amplifier]
分类和应用: 放大器
文件页数/大小: 16 页 / 1953 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
The first place to start is to determine the source resis- Where V  
is the noise due to the external resistors and  
orext  
tance. If it is very small an additional resistance may need is given by:  
to be added to keep the values of R and R to practical  
f
g
2
2
2
F
2
RF  
RF  
levels. For this analysis we assume that R is the total re-  
= e 1 +  
+ e ∗  
+ e  
v
t
n
G
o
RG  
RG  
sistance present on the non-inverting input. This gives us  
one equation that we must solve:  
R = Rg||Rf  
t
The complete equation can be simplified to:  
This equation can be rearranged to solve for R :  
g
2
2
)
2
v
= 3 4kT G RT + e G + 2 i RT  
(
)
(
)
(
R = (R * R ) / (R - R )  
g
t
f
f
t
n n  
o
The other consideration is desired gain (G) which is:  
G = (1 + R /R )  
f
g
It’s easy to see that the effect of amplifier voltage noise  
is proportionate to gain and will tend to dominate at large  
gains. The other terms will have their greatest impact at  
By plugging in the value for R we get  
g
R = G * R  
f
t
large R values at lower gains.  
t
And R can be written in terms of R and G as follows:  
g
t
R = (G * R ) / (G - 1)  
g
t
Layout Considerations  
The complete input offset equation is now only dependent  
on the voltage offset and input offset terms given by:  
General layout and supply bypassing play major roles in  
high frequency performance. CADEKA has evaluation  
boards to use as a guide for high frequency layout and as  
aid in device testing and characterization. Follow the steps  
below as a basis for high frequency layout:  
2
)
2
)
VI  
=
V
+ I RT  
(
(
OS  
IO  
OS  
And the output offset is:  
• Include 6.8µF and 0.1µF ceramic capacitors for power  
supply decoupling  
2
)
2
)
VO  
= G ∗  
V
+ I RT  
(
(
OS  
IO  
OS  
• Place the 6.8µF capacitor within 0.75 inches of the power pin  
• Place the 0.1µF capacitor within 0.1 inches of the power pin  
Noise analysis  
The complete equivalent noise circuit is shown in Figure 7.  
• Remove the ground plane under and around the part,  
especially near the input and output pins to reduce para-  
sitic capacitance  
R
R
f
g
+ –  
+ –  
• Minimize all trace lengths to reduce series inductances  
Refer to the evaluation board layouts below for more in-  
formation.  
R
g
CLC1003  
+
+ –  
+ –  
+
R
L
Evaluation Board Information  
The following evaluation boards are available to aid in the  
testing and layout of these devices:  
Figure 7: Complete Equivalent Noise Circuit  
The complete noise equation is given by:  
Evaluation Board #  
CEB002  
CEB003  
Products  
CLC1003 in SOT23-5  
CLC1003 in SOIC-8  
2
)
2
2
2
2
RF  
RF  
v
=
v
+
e
1 +  
+ i RT 1 +  
+ i RF  
(
o
orext  
n
bp  
bn  
RG  
RG  
©2004-2008 CADEKA Microcircuits LLC  
www.cadeka.com  
14