Data Sheet
Driving Capacitive Loads
3
2
6
G = 10
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
4
1
2
Output
R , between the amplifier and the load to help improve
S
0
0
stability and settling performance. Refer to Figure 5.
Input
-1
-2
-3
-2
-4
-6
Input
+
-
Rs
Output
CL
RL
Rf
0
50
100
150
200
250
300
350
400
450
Rg
Time (us)
Figure 6. Overdrive Recovery
Figure 5. Addition of R for Driving
S
Capacitive Loads
Layout Considerations
Table 1 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in <=1dB
peaking in the frequency response. The Frequency Re-
S
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
sponse vs. C plots, on page 7, illustrates the response of
L
the CLC1001.
C (pF)
L
R (Ω)
S
-3dB BW (MHz)
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
10
22
43
33
20
13
4.3
266
228
192
155
84
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
47
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
100
470
• Minimize all trace lengths to reduce series inductances
Table 1: Recommended R vs. C
S
L
Refer to the evaluation board layouts below for more in-
formation.
For a given load capacitance, adjust R to optimize the
S
tradeoff between settling time and bandwidth. In general,
reducing R will increase bandwidth at the expense of ad-
Evaluation Board Information
S
ditional overshoot and ringing.
The following evaluation boards are available to aid in the
testing and layout of these devices:
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC1001 will typically recover in less than
25ns from an overdrive condition. Figure 6 shows the
CLC1001 in an overdriven condition.
Evaluation Board #
CEB002
CEB003
Products
CLC1001 in SOT23-5
CLC1001 in SOIC-8
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
15