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CDK8307EITQ80 参数 Datasheet PDF下载

CDK8307EITQ80图片预览
型号: CDK8307EITQ80
PDF下载: 下载PDF文件 查看货源
内容描述: 12月13日位,四十零分之二十零/ 50/ 65 / 80MSPS ,八通道,超低功耗ADC LVDS [12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS]
分类和应用:
文件页数/大小: 31 页 / 1408 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Power dissipation savings per channel off  
38  
mW  
Sleep Channel Mode Savings  
Clock Inputs  
65  
MSPS  
MSPS  
Maximum Conversion Rate  
Minimum Conversion Rate  
20  
Electrical Characteristics - CDK8307E  
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Performance  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
68.5  
68  
70.1  
70  
dBFS  
dBFS  
dBFS  
dBFS  
dBc  
SNR  
Signal to Noise Ratio  
69.6  
69.5  
77  
SINAD  
SFDR  
HD2  
Signal to Noise and Distortion Ratio  
Spurious Free Dynamic Range  
Second order Harmonic Distortion  
Third order Harmonic Distortion  
Effective number of Bits  
74  
76  
dBc  
85  
90  
dBc  
90  
dBc  
75  
77  
dBc  
HD3  
76  
dBc  
11.3  
11.3  
bits  
ENOB  
bits  
Crosstalk  
See note (1) on page 13  
95  
dBc  
Power Supply  
173  
88  
mA  
mA  
Analog supply current  
Digital and output driver supply  
Digital supply current  
312  
158  
470  
10  
mW  
mW  
mW  
µW  
Analog power Dissipation  
Digital power Dissipation  
Total power Dissipation  
Power Down Dissipation  
Sleep Mode Dissipation  
Sleep Channel Mode Dissipation  
Sleep Channel Mode Savings  
Power down mode  
Deep sleep mode  
56  
mW  
mW  
mW  
All channels. in sleep ch. mode (light sleep)  
Power dissipation savings per channel off  
116  
44  
Clock Inputs  
80  
MSPS  
MSPS  
Maximum Conversion Rate  
Minimum Conversion Rate  
40  
Digital and Timing Electrical Characteristics  
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Clock Inputs  
Duty Cycle  
Compliance  
20  
80  
%high  
CMOS, LVDS, LVPECL  
±200  
mVpp  
mVpp  
mVpp  
V
Differential input swing  
Input range, differential  
Input range, sine  
±800  
Differential input swing, sine wave clock input  
CLKN connected to ground  
Input range, CMOS  
VOVDD  
Input common mode voltage  
Input capacitance  
0.3  
VOVDD -0.3  
Keep voltages within gnd and voltage of OVDD  
Differential  
2
pF  
©2009 CADEKA Microcircuits LLC  
www.cadeka.com  
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