Data Sheet
Pin Assignments - TQFP
(Continued)
Pin No.
41
42
45
61
62, 64, 66, 67, 69
65
71
72
75
76
77
78
Pin Name
FCLKP
FCLKN
RESETN
TP
NC
VCM
CLKP
CLKN
OVDD
CSN
SDATA
SCLK
Description
LVDS frame clock (1x), positive output
LVDS frame clock (1x), negative output
Reset SPI interface
Test pin. Leave open (un-connected) or connect to GND.
Not connected
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
Serial clock input
CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
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