PRELIMINARY
Data Sheet
Pin Assignments
(Continued)
Pin No.
32
31
30
29
28
27
26
25
24
23
54
55
56
57
58
10
9
40
39
38
TQFP
1, 7, 14, 47, 54, 60, 63, 70
4, 8, 11, 50, 53, 57, 61, 68, 73,
74, 79, 80
2
3
5
6
9
10
12
13
48
49
51
52
55
56
58
59
15, 17, 18, 26, 36, 43, 44, 46
25, 35
AVDD
AVSS
IP1
IN1
IP2
IN2
IP3
IN3
IP4
IN4
IP5
IN5
IP6
IN6
IP7
IN7
IP8
IN8
DVSS
DVDD
Analog power supply, 1.8V
Analog ground
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
Digital and I/O power supply, 1.8V
Pin Name
D6P
D6N
D7P
D7N
D8P
D8N
FCLKP
FCLKN
LCKP
LCKN
NC
NC
VCM
NC
NC
CLKP
CLKN
CSN
SDATA
SCLK
Description
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1X), positive output
LVDS frame clock (1X), negative output
LVDS bit clock, positive output
LVDS bit clock, negative output
Not connected
Not connected
Common mode output pin, 0.5*AVDD
Not connected
Not connected
Positive differential input clock
Negative differential input clock.
Chip select enable. Active Low
Serial data input
Serial clock input
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
Rev 0.4.0
©2009 CADEKA Microcircuits LLC
www.cadeka.com
7
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
