Data Sheet
Applications Dicussion
Figure 5 (on the following page) illustrates a typical CDK3404
interface circuit. In this example, an optional 1.2V band-
gap reference is connected to the V
REF
output, overriding
the internal voltage reference source.
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the CDK3404,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer
to the CDK3404 and its related analog circuitry can
have an adverse effect on performance.
5. CLK should be handled carefully. Jitter and noise on this
clock will degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.
CDK3404
8-bit, 180MSPS, Triple Video DACs
Grounding
It is important that the CDK3404 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video
signals at the output of the circuit. The CDK3404 has
separate analog and digital circuits. To keep digital system
noise from the D/A converter, it is recommended that power
supply voltages come from the system analog power
source and all ground connections (GND) be made to the
analog ground plane. Power supply pins should be indi-
vidually decoupled at the pin.
Improved Transisiton Times
Output shunt capacitance dominates slowing of output
transition times, whereas series inductance causes a small
amount of ringing that affects overshoot and settling time.
With a doubly terminated 75Ω load, transition times can
be improved by matching the capacitive impedance output
of the CDK3404. Output capacitance can be matched with
a 220nH inductor in series with the 75Ω source termination.
IO
G
32
W1
COAX
R1
75Ω
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog circuits
may result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1. Keep the critical analog traces (V
REF
, I
REF
, COMP, IO
S
,
IO
R
, IO
G
) as short as possible and as far as possible
from all digital signals. The CDK3404 should be
located near the board edge, close to the analog out-put
connectors.
2. The power plane for the CDK3404 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the V
DD
pins. If
the power supply for the CDK3404 is the same
as that of the system’s digital circuitry, power to the
CDK3404 should be decoupled with 0.1µF and
0.01µF capacitors and isolated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
U1
CDK3404
IO
B
29
W2
COAX
R2
75Ω
Rev 3A
IO
R
33
W3
COAX
R3
75Ω
L1
220nH
R4
75Ω
L2
220nH
R5
75Ω
L3
220nH
R6
75Ω
Figure 4. Schematic, Transition Time Sharpening Circuit
A 220nH inductor trims the performance of a 4ft cable,
quite well. In Figures xx through xx, the glitch at 12.5ns, is
due to a reflection from the source. Not shown, are smaller
glitches at 25 and 37.5ns, corresponding to secondary and
tertiary reflections. Inductor values should be selected to
match the length and type of the cable.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
9
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
