Data Sheet
Applications Dicussion
Figure 9 below illustrates a typical CDK3402/3403 interface
circuit. In this example, an optional 1.2V bandgap refer-
ence is connected to the V
REF
output, overriding the inter-
nal voltage reference source.
Grounding
It is important that the CDK3402/3403 power supply is well-
+5V
10µF
0.1µF
VDD
RED PIXEL
INPUT
GREEN PIXEL
INPUT
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
R7-0
GND
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video
signals at the output of the circuit. The CDK3402/3403 has
separate analog and digital circuits. To keep digital system
noise from the D/A converter, it is recommended that
power supply voltages (V
DD
) come from the system analog
power source and all ground connections (GND) be made
to the analog ground plane. Power supply pins should be
individually decoupled at the pin.
CDK3402/CDK3403
8-bit, 100/150MSPS, Triple Video DACs
IO
R
IO
G
75Ω
75Ω
75Ω
COMP
0.1µF
V
REF
R
REF
+5V
Red
Z
o
= 75Ω
75Ω
75Ω
75Ω
Green w/Sync
Z
o
= 75Ω
G7-0
B7-0
CLK
SYNC
BLANK
Blue
Z
o
= 75Ω
CDK3402/3403
Triple 8-bit D/A Converter
IO
B
(not required without external reference)
3.3kΩ
LM185-1.2
590Ω
(Optional)
0.1µF
Figure 9. Typical Interface Circuit Diagram
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog circuits
may result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1. Keep the critical analog traces (V
REF
, I
REF
, COMP, IO
S
,
IO
R
, IO
G
) as short as possible and as far as possible
from all digital signals. The CDK3402/3403 should be
located near the board edge, close to the analog out-put
connectors.
2. Power plane for the CDK3402/3403 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the V
DD
pins. If
the power supply for the CDK3402/3403 is the same
as that of the system’s digital circuitry, power to the
CDK3402/3403 should be decoupled with 0.1µF and
0.01µF capacitors and iso-lated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the CDK3402/3403,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer
to the CDK3402/3403 and its related analog circuitry can
have an adverse effect on performance.
5. CLK should be handled carefully. Jitter and noise on this
clock will degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.
Evaluation boards are available (CEB3402 and CEB3403),
contact CADEKA for more information.
Rev 1B
Related Products
CDK3400/3401 Triple 10-bit 100/150MSPS DACs
n
CDK3404 Triple 8-bit 180MSPS DAC
n
©2008 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
