Data Sheet
Pin Assignments
(Continued)
Pin No.
30
31
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
59
60, 61
Pin Name
D1_4
D1_5
D1_6
D1_7
D1_8
D1_9
D1_10
D1_11
D1_12
ORNG_1
CLK_EXT
D0_0
D0_1
D0_2
D0_3
D0_4
D0_5
D0_6
D0_7
D0_8
D0_9
D0_10
D0_11
D0_12
ORNG_0
OE_N_0
CM_EXTBC_1,
CM_EXTBC_0
SLP_N_1,
SLP_N_0
Description
Output Data Channel 1
Output Data Channel 1
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1 (MSB for 1V
pp
full scale range, see Reference Voltages section)
Output Data Channel 1 (MSB for 2V
pp
full scale range)
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels.
Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)
Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0 (MSB for 1V
pp
full scale range, see Reference Voltages section)
Output Data Channel 0 (MSB for 2V
pp
full scale range)
Out of Range flag Channel 0. High when input signal is out of range.
Output Enable Channel 0. Tristate when low.
Bias control bits for the buffer driving pin CM_EXT
00: Off
01: 50uA
10: 500uA
11: 1mA
Sleep Mode
00: Sleep Mode
10: Channel 1 active
01: Channel 0 active
11: Both channels active
62, 63
Rev 2B
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
