Data Sheet
Electrical Characteristics
(T = T = T = +25°C , V = -5.2V, V = -2.0V, V = -1.0V, V = 0.00V, ƒ = 750MHz, Duty Cycle=50%,
J
C
A
EE
RB
RM
RT
CLK
unless otherwise specified)
cDK1302a
cDl1302B
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Resolution
8
8
bits
DC Performance
DLE
ILE
Differential Linearity Error(1)
Integral Linearity Error(1)
No Missing Codes
ƒclk = 100MHz
ƒclk = 100MHz
-1.0
+1.0
-1.5
+1.5
+1.5
LSB
LSB
-0.85
+0.95
-0.95
Guaranteed
Guaranteed
Analog Input
Input Voltage Range(1)
Input Bias Current(1)
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
VRB
VRT
2.0
VRB
VRT
2.0
V
VIN = 0V
0.75
15
0.75
15
mA
kΩ
pF
Over Full Input Range
15
15
900
500
900
500
MHz
MHz
mV
Large Signal
Offset Error(2)
Offset Error(2)
VRT
VRB
-30
-30
+30
+30
-30
-30
+30
+30
mV
Input Slew Rate
5
2
5
2
V/ns
μA
Clock Synchronous Input Currents
Reference Input
Ladder Resistance(1)
Reference Bandwidth
60
80
30
60
80
30
Ω
MHz
Timing Characteristics
Maximum Sample Rate(1)
750
750
MHz
ps
Aperture Jitter
2
2
Acquisition Time
250
1.4
250
1.4
ps
CLK to Data Delay(2)
CLK to Data Ready Delay(2)
0.9
1.9
0.9
1.9
ns
1.25
1.75
2.25
1.25
1.75
2.25
ns
Dynamic Performance
ƒIN = 50MHz(1)
ƒIN = 250MHz(1)
ƒIN = 50MHz(1)
ƒIN = 250MHz(1)
ƒIN = 50MHz(1)
ƒIN = 250MHz(1)
ƒIN = 50MHz(1)
ƒIN = 250MHz(1)
46
44
44
42
dB
dB
SNR
Signal-to-Noise Ratio
-45
-37
48
-43
-35
44
dBc
dBc
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
SFDR
SINAD
40
36
dB
43
41
dB
36
34
dB
nꢀꢅꢄꢈ:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
3. Typical Thermal Impedance: θ = +4°C/W.
JC
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
