Data Sheet
Pin Configuration
TQFP-44
CDK1301
8-bit, 250 MSPS A/D Converter with Demuxed Outputs
CDK1301
Pin Assignments
Pin No.
40
39
16-9
19-26
28
27
4
3
5
6
Pin Name
V
IN+
V
IN-
DA
0
–DA
7
DB
0
–DB
7
DCLK
OUT
DCLK
OUT
CLK
CLK
RESET
RESET
Description
Non-inverted analog input; nominally 1V
pp
; 100k pullup to V
cc
and 100k pulldown to AGND, internally
Inverted analog input; nominally 1V
pp
; 100k pullup to V
cc
and 100k pulldown to AGND, internally
Data output bank A; 3V/5V LVCMOS compatible
Data output bank B; 3V/5V LVCMOS compatible
Non-inverted data output clock; 3v/5v 3V/5V LVCMOS compatible
Inverted data output clock; 3V/5V LVCMOS compatible
Non-inverted clock input pin; 100k pulldown to AGND, internally
Inverted clock input pin; 17.5k pullup to V
cc
and 7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data output bank relationship when in dual channel
mode (DMODE
1
= 0); 100k pulldown to AGND, internally
Inverted RESET input pin; 17.5k pullup to V
cc
and 7.5 pulldown to AGND, internally
Internally: 100k pulldown to AGND on DMODE
1
50k pullup to V
cc
on DMODE
2
32, 31
DMODE
1,2
Data output mode pins: DMODE
1
= 0, DMODE
2
= 0: parallel dual channel output
DMODE
1
= 0, DMODE
2
= 1: interleaved dual channel output
DMODE
1
= 1, DMODE
2
= x: single channel data output on bank a (125 MSPS max)
2
37
35, 36,
42, 43
7, 17, 30
1, 33, 34,
38, 41, 44
8, 18, 29
PD
V
CM
AV
CC
OV
DD
AGND
DGND
Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down
mode; 100k pulldown to AGND, internally
2.5V common mode voltage reference output
+5V analog supply
+3V/+5V digital output supply
Analog ground
Digital ground
REV 1A
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