CDK1308_09 参数 Datasheet PDF下载

Data Sheet

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,

-1dBFS 8MHz input signal, unless otherwise noted)

Symbol

DC Accuracy

Parameter

No Missing Codes

Offset Error

Gain Error

Conditions

Min

Typ

Guaranteed

Max

Units

CDK1308

Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs

Midscale offset

Full scale range deviation from typical

-6

1

6

±0.15

±0.2

V

AVDD

/2

LSB

%FS

LSB

LSB

V

V

CM

+0.2

V

V

pp

pF

MHz

DNL

INL

V

CMO

Differential Non-Linearity

Integral Non-Linearity

Common Mode Voltage Output

Input Common Mode

Full Scale Range

Input Capacitance

Bandwidth

Analog input common mode voltage

Differential input voltage range

Differential input capacitance

Input bandwidth, full power

Supply voltage to all 1.8V domain pins.

See Pin Configuration and Description

Output driver supply voltage (OVDD).

Must be higher than or equal to Core Supply

Voltage (V

OVDD

≥ V

DVDD

)

500

1.7

1.7

V

CM

-0.1

Analog Input

V

CMI

V

FSR

2.0

2.0

Power Supply

AVDD,

DVDD

OVDD

Core Supply Voltage

I/O Supply Voltage

1.8

2.5

2.0

3.6

V

V

Rev 1A

©2009 CADEKA Microcircuits LLC

www.cadeka.com

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