BS616LV2019
n
PIN DESCRIPTIONS
Name
A0-A16 Address Input
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
Function
These 17 address inputs select one of the 262,144 x 16 bit in the RAM
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected. (48B BGA ignore CE2 pin)
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE
H
X
X
L
CE2
(1)
X
L
X
H
H
WE
X
X
X
H
H
OE
X
X
X
H
H
LB
X
X
H
L
X
L
UB
X
X
H
X
L
L
L
H
L
L
H
DQ0~DQ7 DQ8~DQ15 V
CC
CURRENT
High Z
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
High Z
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
L
Read
L
H
H
L
H
L
L
Write
L
H
L
X
H
L
1. 48BGA ignore CE2 condition.
2. H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BS616LV2019
2
Revision 1.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
