BS616LV1010
n PIN DESCRIPTIONS
Name
Function
These 16 address inputs select one of the 65,536 x 16-bit in the RAM
A0-A15 Address Input
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
There 16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
IO0~IO7
High Z
High Z
High Z
High Z
DOUT
IO8~IO15
High Z
High Z
High Z
High Z
DOUT
VCC CURRENT
CE
H
WE
X
OE
X
LB
X
H
L
UB
X
H
X
L
ICCSB, ICCSB1
Chip De-selected
(Power Down)
X
X
X
ICCSB, ICCSB1
L
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Output Disabled
Read
L
H
H
X
L
L
L
L
H
L
L
H
L
L
High Z
DOUT
DOUT
H
L
High Z
DIN
L
DIN
Write
X
H
L
L
X
DIN
H
DIN
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
Revision 2.6
R0201-BS616LV1010
2
May.
2006