TISP61089B High Voltage Ringing SLIC Protector
Gated Protectors (Continued)
protection voltage, the length of the capacitor to gate terminal tracking should be minimized. Inductive voltages in the protector cathode wiring
will also increase the protection voltage. These voltages can be minimized by routing the SLIC connection through the protector as shown in
Figure 6.
Figure 9, which has a 10 A/µs rate of impulse current rise, shows a positive gate charge (Q
GS
) of about 0.1
µC.
With the 0.1
µF
gate
decoupling capacitor used, the increase in gate supply is about 1 V (= Q
GS
/C1). This change is just visible on the -72 V gate voltage, V
BATH
.
But, the voltage increase does not directly add to the protection voltage as the supply voltage change reaches a maximum at 0.4
µs,
when the
gate current reverses polarity, and the protection voltage peaks earlier at 0.3
µs.
In Figure 9, the peak clamping voltage (V
(BO)
) is -77.5 V, an
increase of 5.5 V on the nominal gate supply voltage. This 5.5 V increase is the sum of the supply rail increase at that time, (0.5 V), and the
protection circuit’s cathode diode to supply rail breakover voltage (5 V). In practice, use of the recommended 220 nF gate decoupling capacitor
would give a supply rail increase of about 0.3 V and a V
(BO)
value of about -77.3 V.
0
Voltage - V
-20
VK
VBATH
-40
-60
-80
0.0
0.5
Time -
µs
AI6XDE
1.0
1.5
1
0
QGS
IG
Current - A
-1
-2
-3
-4
-5
0.0
0.5
Time -
µs
1.0
1.5
IK
Figure 9. Protector Fast Impulse Clamping and Switching Waveforms
Voltage Stress Levels on the TISP61089B
Figure 10 shows the protector electrodes. The package terminal designated gate, G, is the transistor base, B, electrode connection and so is
marked as B (G). The following junctions are subject to voltage stress: Transistor EB and CB, SCR AK (off state) and the antiparallel diode
(reverse blocking). This clause covers the necessary testing to ensure the junctions are good.
Testing transistor CB and EB:
The maximum voltage stress level for the TISP61089B is V
BATH
with the addition of the short term antiparallel
diode voltage overshoot, V
FRM
. The current flowing out of the G terminal is measured at V
BATH
plus V
FRM
. The SCR K terminal is shorted to
the common (0 V) for this test (see Figure 10). The measured current, I
GKS
, is the sum of the junction currents I
CB
and I
EB
.
OCTOBER 2000 - REVISED JULY 2008
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
BOURNS [ BOURNS ELECTRONIC SOLUTIONS ]
