3.22 Watchdog Timer
There are three access cycles of Watch-Dog Timer as Enable, Refresh
and Disable are the three access cycles of Watchdog Timer. The
Enable cycle proceeds via READ PORT 443H whereas the Disable
cycle proceeds via READ PORT 045H. A continued Enable cycle after
a first Enable cycle means Refresh.
Once the Enable cycle is active, a Refresh cycle is requested before
the time-out period. This restarts counting of the WDT period. When
the time counting goes over the period preset of WDT, it will assume
that the program operation is abnormal. A System Reset signal to
re-start or a NMI cycle to the CPU transpires when such error happens.
Jumper JP6 is used to select the function of Watchdog Timer.
ꢂ JP6: Watchdog Timer Active Type Setting
Options
Settings
Active NMI
System Reset
* Disabled Watchdog Timer
Short 1-2
Short 2-3
Open
ꢂ JP4(5-10): WDT Timeout Period Select
Period
PINS 5-6 PINS 7-8 PINS 9-10
* 1 sec
2 sec
10 sec
20 sec
110 sec
220 sec
Short
Open
Short
Open
Short
Open
Short
Short
Open
Open
Short
Short
Short
Short
Short
Short
Open
Open
The Watchdog Timer is disabled after the system Power-On. It can be
enabled via an Enable cycle and reading the control port (443H), or via
a Refresh cycle and reading the control port (443H), or via a Disable
cycle and reading the disable control port (045H).
After an Enable cycle of WDT, user must immediately execute a
Refresh cycle to WDT before its period setting comes to an end every
1, 2, 10, 20, 110 or 220 seconds. If the Refresh cycle does not activate
before WDT period cycle, the onboard WDT architecture will issue a
Reset or NMI cycle to the system. There are three I/O ports that control
the Watchdog Timer.
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