ꢃ JP9: Watchdog Timer Active Type Select
1
3
JP9
Description
Short 1-2 (default)
Short 2-3
System Reset
Active NMI
Disabled
Open
ꢃ JP14: Watchdog Timer Out Period Select
Period PINS 1-2 PINS 3-4 PINS 5-6 PINS 7-8
1 sec
Open
Open
Short
Open
(default)
2 sec
2
1
8
7
Open
Open
Open
Short
Short
Open
Short
Short
Open
Open
Short
Open
Open
Open
Open
Short
Open
Short
Open
Short
10 sec
20 sec
110 sec
220 sec
The watchdog timer is disabled after the system power-on. The
watchdog timer can be enabled by a Enable cycle with reading the
control port (443H), a Refresh cycle with reading the control port
(443H) and a Disable cycle by reading the watchdog timer disable
control port (043H). After a Enable cycle of WDT, user must constantly
proceed a Refresh cycle to WDT before its period setting comes ending
of every 1, 2, 10, 20, 110 or 220 seconds (Please reference to the
selection table of JP14 for WDT Time Out period setting). If the Refresh
cycle does not active before WDT period cycle, the onboard WDT
architecture will issue a Reset or NMI cycle to the system. The
watchdog timer controlled by two I/O ports.
443H
043H
I/O Read
I/O Read
Enable/Refresh cycle
Disable cycle
The following sample program shows how to Enable, Disable and
Refresh the watchdog timer：
WDT_EN_RF
EQU
0433H
0043H
WDT_DIS
EQU
WT_Enable
PUSH
DX
AX
; keep AX DX
PUSH
MOV
IN
DX,WDT_EN_RF ; enable the WDT
AL,DX
POP
POP
RET
DX
AX
; get back AX, DX
11
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