BMA253
Data sheet
Page 46
5.2 FIFO Data Readout
The FIFO stores the data that are also available at the acceleration read-out registers (0x02) to
(0x07). Thus, all configuration settings apply to the FIFO data as well as the acceleration data
readout registers. The FIFO read out is possible through register (0x3F). The readout can be
performed using burst mode since the read address counter is no longer incremented, when it
has reached address (0x3F). This implies that the trapping also occurs when the burst read
access starts below address (0x3F). A single burst can read out one or more frames at a time.
Register (0x3E) fifo_data_select controls the acceleration data of which axes are stored in the
FIFO. Possible settings for register (0x3E) fifo_data_select are ‘00b’ for x, y- and z-axis, ‘01b’
for x-axis only, ‘10b’ for y-axis, ‘11b’ for z-axis only. The depth of the FIFO is independent of
whether all or a single axis have been selected. Writing to register (0x3E) clears the buffer
content and resets the FIFO-full and watermark interrupts.
If all axes are enabled, the format of the data read-out from register (0x3F) is as follows:
X LSB
X MSB
Y LSB
Y MSB
Z LSB
Z MSB
…
…
Frame 1
If only one axis is enabled, the format of the data read-out from register (0x3F) is as follows
(example shown: y-axis only, other axes are equivalent).
…
Y LSB
Y MSB
Y LSB
Y MSB
Frame 1
Frame 2
If a frame is not completely read due to an incomplete read operation, the remaining part of the
frame is discarded. In this case the FIFO aligns to the next frame during the next read
operation. In order for the discarding mechanism to operate correctly, there must be a delay of
at least 1.5 us between the last data bit of the partially read frame and the first address bit of the
next FIFO read access. Otherwise frames must not be read out partially.
If the FIFO is read beyond the FIFO fill level zeroes (0) will be read. If the FIFO is read beyond
the FIFO fill level the read or burst read access time must not exceed the sampling time tSAMPLE
.
Otherwise frames may be lost.
5.3 FIFO Frame Counter and Overrun Flag
Register (0x0E) fifo_frame_counter reflects the current fill level of the buffer. If additional frames
are written to the buffer although the FIFO is full, the (0x0E) fifo_overrun bit is set to ‘1’. The
FIFO buffer is cleared, the FIFO fill level indicated in register (0x0E) fifo_frame_counter and the
(0x0E) fifo_overrun bit are both set to ‘0’ each time one a write access to one of the FIFO
configuration registers (0x3E) or (0x30) occurs. The (0x0E) fifo_overrun bit is not reset when
the FIFO fill level (0x0E) fifo_frame_counter has decremented to ‘0’ due to reading from register
(0x3F).
BST-BMA253-DS000-01 | Revision 1.0 | August 2015
Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
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