BL8082
be limited within 1W, LDO2 power dissipation is
recommended to be limited within 1W, and total
power dissipation is recommended to be limited
within 2W. Due to the overall power consumption
and heat of the chip, the individual pathway may
not reach the maximum current due to
temperature protection.
to help cool the IC to further improve
efficiency and long-term reliability. The
proposed VIN1 and VO1 copper clad area of
over 200 square mm (2 oz thickness).
5) Ensure all feedback connections are short and
direct. Place the feedback resistors as close to
the IC as possible.
6) Route high-speed switching nodes away from
sensitive analog areas.
APPLICATION INFORMATION
Layout is critical to achieve clean and stable
operation. The switching power stage and heat
dissipation requires particular attention. Follow
these guidelines for good PC board layout:
1) Place decoupling capacitors as close to the IC
as possible
2) Connect input and output capacitors to the
same power ground node with a star ground
configuration then to IC ground.
3) Keep the high-current paths as short and wide
as possible. Keep the path of switching current
(CIN to VIN and CIN to GND) short. Avoid vias
in the switching paths.
Fig1. DEMO PCB (Unit:mm)
4) If possible, connect VIN1, VO1, VIN2, VO2, VIN,
SW, and GND separately to a large copper area
PACKAGE OUTLINE
Package
DFN3X3-12
Devices per reel
3000
Unit
mm
Package specification：
www.belling.com.cn
6
BELLING [ BELLING ]
