BL7442LV Low voltage
Intelligent 2K bits EEPROM
(all values at 50 kHZ clock rate)
Command Entry
Processing
CLK
I/O
1
2
1
3
2
24
1
2
3
m
m-1
m-2
24
RST
Figure 7 Update Main Memory
Update Security Memory
Regarding the reference data bytes this command will only be executed if a PSC has been
successfully verified before. Otherwise only each bit of the error counter (Address 0)can be
written from “1” to “0”.The execution times and the required clock pulses are the same as
described under Update Main Memory.
Write Protection Memory
The execution of this command contains a comparison of the entered data byte with the assigned
byte in the EEPROM .In case of identity the protection bit is written thus making the data
information unchangeable. If the data comparison results in data differences writing of the
protection bit will be suppressed. Execution times and required clock pulses see Update Main
Memory.
Compare Verification Data
This command can only be executed in combination with an update procedure of the error
counter(see Usage of Compare Command).The command compares one byte of the entered
verification data byte with the corresponding reference data byte. For this procedure clock pulses
are necessary during the processing mode.
A type: Before data comparison , I/O pin is high impedance. Because the data of error counter
(EC) can not be read, the identification of EC is different from BL7442. After power on, whatever
EC is in which state, it is considered to 111(07H), Then the EC is written one bit and compared
one time, After comparison is correct(can be read out the content of PSC),it will be written back to
07H.If original data of EC is 07H, it is same as type B. If original data of EC is not 07H,the
security code verification is unsuccessful. Although security code is correct, EC operation is of no
effect when EC is equal to 01H or 03H. Both A and B type the internal operation is same. The
difference between type A and type B is only type A can not be read out the content of EC.
B type: It is same as BL7442.
Usage of the Compare Command
The following procedure has to be carried out exactly as described. Any variation leads to a
failure so that a write/erase access will not be achieved. As long as the procedure has not been
successfully concluded the error counter bits can only be changed from “1” to “0” but not erased.
All first an error counter bit has to be written to “0” by an UPDATE command (see figure
8)followed by three COMPARE VERIFICATION DATA commands beginning with byte 1 of the
reference data. A successful conclusion of the whole procedure can be recognized by being able
to erase the error counter which is not automatically erased. Now write/erase access to all
memory areas is possible as long as the operating voltage is applied. In case of error the whole
procedure can be repeated as long as erased counter bits are available. Having been enabled,
the reference data are allowed to be altered like any other information in the EEPROM.
As shipped, the PSC is programmed with a code according to individual agreement with the
customer. Thus, knowledge of this code is indispensable to alter data.
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8/16/2006
Total 10 Pages
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