BL7432SM Low voltage Intelligent 2K bits
EEPROM
The transmission protocol consists of the 4 modes:
1) Reset and Answer-to-Reset
2) Command Mode
3) Outgoing Data Mode
4) Processing Mode
(1) Reset and Answer-to-Reset
Answer-to-Reset takes place according to ISO standard 7816-3. The reset can be given at
any time during operation. In the beginning, the address counter id set to zero together with a
clock pulse and the first data bit (LSB) is output to I/O when RST is set from state H to state L.
Under a continuous input of additional 31 clock pulses the contents of the first 4 EEPROM
rd
addresses can be read out. The 33 clock pulse switches I/O to state H (figure 3). During
Answer-to-Reset any start and stop condition is ignored.
VCC
RST
1
CLK
1
I/O
2
3
...
30
31
32
2
3
4
...
31
32
RST
td4
td4
tH
tL
CLK
td2
I/O
td5
Figure 3 Reset and Answer-to-Reset
(2) Command Mode
After the Answer-to-Reset the chip waits for a command. Every command begins with a start condition,
includes a 3 bytes long command entry followed by an additional clock pulse and ends with a stop condition
(figure 4).
--Start condition: Falling edge on I/O during CLK in state H
--Stop condition: Rising edge on I/O during CLK in state H
Command
1
CLK
2
3
4
23
24
IFD sets I/O to State L
I/O
START
From IFD
CLK
td1
tBUF
I/O
tF
td7
STOP
From IFD
tR
td5
td8
td3
tL
Figure 4 Command Mode
http://www.belling.com.cn
-3-
Total
8 Pages
5/18/2010
Wrote by ICCD
BELLING [ SHANGHAI BELLING CO., LTD. ]
