4位MASK LCD型单片机芯片BL2456
INT1 is selectable.
Only INT0 is synchronized with
the system clock.
INT2
I
Quasi-interrupt with detection 19
of rising edge signals.
P1.2
Input
Input
A-4
D
KS0–KS3
I/O
Quasi-interrupt
input
with 29-32 P6.0-P6.3
falling edge detection.
CPU clock output.
CLO
BUZ
I/O
I/O
23
P2.2
P2.3
Input
Input
D
D
2, 4, 8or16kHzfrequencyoutput 24
for buzzer sound with 4.19 MHz
main system clock or 32.768 kHz
subsystem clock.
XIN, XOUT
-
-
Crystal,ceramicorRCoscillator 12,11
pins for main system clock.
For external clock input, use XIN
and input XIN’s reverse phase to
XOUT.
-
-
-
-
-
-
XTIN, XTOUT
Crystal oscillator pins for 14,15
subsystem clock.
For external clock input, use
XTIN and input XTIN’s reverse
phase to XTOUT.
VDD
-
-
-
-
Main power supply.
Ground.
9
-
-
-
-
-
-
-
B
-
VSS
10
16
13
-
RESET
TEST
Reset signal.
Input
-
Test signal input (must be
connected to VSS).
注：当I / O 端口被设值为输出模式时上拉电阻自动禁止。
管脚电路图：
Type A
Type C
http://www.belling.com.cn
- 4 -
8/24/2006
Total 11 Pages
Wrote by dipeng
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