Preliminary Datasheet
VOLTAGE DETECTOR
AZ70XX
AZ70XX
Operating Diagram (Continued)
Figure 12 is a typical timing waveform for AZ70XX
during power-up and temporary power-down period.
Here is some explanations for AZ70XX's operation.
3. During power-down, after a delay time of tpHL
from the moment V <V -V
, V
will be at its
CC
S
HYS
OUT
logic low state. In general, at rated output current and
can be pulled down to a voltage as low as
V
V
CC, OUT
1. During power-up period, V
will remain
rises above V (typically
OPR
OUT
within 0.4V from GND. (See the Electrical
Characteristics section).
undefined until V
CC
0.8V). After that moment, the output will become
valid and will be at its logic low state while
4. V
will be at its logic low state while V -
S
OUT
V
<V <V for power-up operating.
V
>V >V
for power-down operating.
OPR
OPR
CC S
HYS
CC
2. After a delay time of tpLH from the moment
>V , the V will be at its logic high state. In
5. After V
falls below V
, the output is
OPR
CC
V
CC
S
OUT
undefined.
general, V
is dependent upon the voltage that the
OUT
pull up resistor connected to.
Typical Applications
VCC +5V
VCC
R1
3.3k
R1
220
1
VCC
3
1
VCC
VCC
CPU
GND
3
AZ70XX
OUT
AZ70XX
OUT
RESET
+
GND
GND
2
LED
2
C1
1 µF
Figure 13. Low Voltage Indicator
Figure 14. CPU Resetting Circuit
BCD Semiconductor Manufacturing Limited
Jul. 2005 Rev. 1. 3
9
BCDSEMI [ BCD SEMICONDUCTOR MANUFACTURING LIMITED ]
