σO = 6µA
Upper Range: From equation (11), the predominant errors
are IOS RTO (6µA), VOS RTI (30µV), and IB (150nA), max, B
grade. Both IOS and VOS can be trimmed to zero; however,
the result is an error of 0.09% of span instead of 0.19% span.
σ1 = 30µV + (150nA X 47Ω + 20nA X 190Ω)
7720mV
3.16 X 105
0.1325V
3.16 X 103
+
+
= 30µV + 9.23µV + 24µV + 4.19µV
= 67.42µV
RECOMMENDED HANDLING
PROCEDURES FOR INTEGRATED CIRCUITS
All semiconductor devices are vulnerable, in varying
degrees, to damage from the discharge of electrostatic
energy. Such damage can cause performance degradation or
failure, either immediate or latent. As a general practice, we
recommend the following handling procedures to reduce the
risk of electrostatic damage.
σS = 0.0001
eIN = e'2 – V4 = IREF1 RT 150°C – IREF2 R4
= (1mA X 156.4Ω) – (1mA X 109Ω) = 47mV
IO error = σO + K σI + K σS eIN = 6µA +
Ω
Ω
(0.34 X 67.42µV) + (0.34 X 0.0001
X 47000µV) = 6µA + 22.92µA + 1.60µA
= 30.52µA
1. Remove the static-generating materials, such as untreated
plastic, from all areas that handle microcircuits.
30.52µA
2. Ground all operators, equipment, and work stations.
% error =
X 100%
16mA
= 0.19% of span at upper range value.
3. Transport and ship microcircuits, or products incorporat
ing microcircuits, in static-free, shielded containers.
4. Connect together all leads of each device by means of a
conductive material, when the device is not connected
into a circuit.
CONCLUSIONS
Lower Range: From equation (10) it is observed that the
predominant error term is the input offset voltage (30µV for
the B grade). This is of little consequence in many applica-
tions. VOS RTI can, however, be nulled using the pot shown
in Figures 5 and 6. The result is an error of 0.06% of span
instead of 0.13% if span.
5. Control relative humidity to as high a value as practical
(50% recommended).
®
15
XTR101
BB [ BURR-BROWN CORPORATION ]
