Some applications select gain of the PGA204/205 with
switches or jumpers. Figure 2 shows pull-up resistors con-
nected to assure a noise-free logic “1” when the switch,
jumper or open-collector logic is open or off. Fixed-gain
applications can connect the logic inputs directly to V+ or
V– (or other valid logic level); no resistor is required.
V+
4
Over-Voltage
Protection
–
A1
VIN
100kΩ
100kΩ
16
Digitally Selected
Feedback Network
15
14
OFFSET VOLTAGE
Voltage offset of the PGA204/205 consists of two compo-
nents—input stage offset and output stage offset. Both
components are specified in the specification table in equa-
tion form:
+
A2
VIN
Over-Voltage
Protection
5
Switches, jumpers
or open-collector
logic output.
6
7
9
Digital ground can
alternatively be connected
to V– power supply.
VOS = VOSI + VOSO / G
where:
(1)
VOS
Adj
VO2
VOS total is the combined offset, referred to the input.
FIGURE 2. Switch or Jumper-Selected Digital Inputs.
VOSI is the offset voltage of the input stage, A1 and A2.
VOSO is the offset voltage of the output difference
amplifier, A3.
1.3mA flows in the digital ground pin. It is good practice to
return digital ground through a separate connection path so
that analog ground is not affected by the digital ground
current.
VOSI and VOSO do not change with gain. The composite
offset voltage VOS changes with gain because of the gain
term in equation 1. Input stage offset dominates in high gain
(G≥100); both sources of offset may contribute at low gain
(G=1 to 10).
The digital inputs, A0 and A1, are not latched; a change in
logic inputs immediately selects a new gain. Switching time
of the logic is approximately 1µs. The time to respond to
gain change is effectively the time it takes the amplifier to
settle to a new output voltage in the newly selected gain (see
settling time specifications).
OFFSET TRIMMING
Both the input and output stages are laser trimmed for very
low offset voltage and drift. Many applications require no
external offset adjustment.
Many applications use an external logic latch to access gain
control data from a high speed data bus (see Figure 7). Using
an external latch isolates the high speed digital bus from
sensitive analog circuitry. Locate the latch circuitry as far as
practical from analog circuitry.
Figure 3 shows an optional input offset voltage trim circuit.
This circuit should be used to adjust only the input stage
offset voltage of the PGA204/205. Do this by programming
VO1 V+
1
13
PGA204
PGA205
–
VIN
4
Over-Voltage
Protection
Feedback
A1
12
25kΩ
25kΩ
Resistors can be substituted
for REF200. Power supply
rejection will be degraded.
16
A1
A0
Digitally Selected
Feedback Network
A3
15
14
11
VO = G (VI+N – VI–N) + VREF
V+
Digital
Ground
100µA
VREF
A2
1/2 REF200
+
VIN
5
Over-Voltage
Protection
10
25kΩ
25kΩ
100Ω
100Ω
OPA177
6
7
9
8
10kΩ
±10mV
Adjustment Range
VO2
V–
Input Offset
200kΩ
to 1MΩ
Output Offset
Adjustment
Adjustment
Trim Range
≈ ±250µV
100µA
1/2 REF200
V+
V–
FIGURE 3. Optional Offset Voltage Trim Circuit.
®
11
PGA204/205
BB [ BURR-BROWN CORPORATION ]
