communications between the PCM1800 and the digital au-
dio processor or external circuit. While in the case of the
Slave Mode, the PCM1800 receives the timing of data
transfer from an external controller.
RESET
PCM1800 has both an internal power-on reset circuit and an
external forced reset (RSTB, pin 6). The internal power-on
reset initializes (resets) when the supply voltage (VCC/VDD
)
exceeds 4.0V (typ). To initiate the reset sequence externally,
apply a logic level LOW to the RSTB pin.
MODE1
MODE0
INTERFACE MODE
The RSTB pin is terminated by an internal pull-down
resistor. If the RSTB pin is unconnected, the ADC will
remain in the reset state. During VCC/VDD < 4.0V (typ),
0
0
1
1
0
1
0
1
Slave Mode (256/384/512fS)
Master Mode (512fS)
Master Mode (384fS)
Master Mode (256fS)
RSTB = LOW and 1024 system clock periods after VCC
/
VDD 4.0V and RSTB = HIGH. The PCM1800 stays in the
reset state and the digital output is forced to zero. The
digital output is valid after reset state release and 18436fS
periods. During reset, the logic circuits and the digital
filter stop operating. Figures 3 and 4 illustrate the internal
power-on reset and external reset timing.
TABLE II. Interface Modes.
Master Mode
In the Master Mode, BCK, LRCK, and FSYNC are output
pins and are controlled by timing generated in clock cir-
cuitry of the PCM1800.
FSYNC is used to designate the valid data from the PCM1800.
The rising edge of FSYNC indicates the starting point of the
converted audio data and the following edge of this signal
indicates the ending points of data. The frequency of this
signal is fixed at 2xLRCK and duty cycle ratio depends on
data bit length. The frequency of BCK is fixed at 64X
LRCK.
SERIAL AUDIO DATA
INTERFACE
The PCM1800 interfaces the audio system through BCK (pin
14), LRCK (pin 13), FSYNC (pin 12) and DOUT (pin 15).
INTERFACE MODE
The PCM1800 supports Master and Slave Modes as inter-
face modes and are selected by MODE1 (pin 11) and
MODE0 (pin 10), as shown in Table II. In case of the Master
Mode, the PCM1800 provides the timing of serial audio data
Slave Mode
In Slave Mode, BCK, LRCK, and FSYNC are input pins.
FSYNC is used to enable BCK signal, and the PCM1800 can
shift out the converted data when FSYNC is HIGH.
4.4V
4.0V
3.6V
VCC/VDD
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock Periods
FIGURE 3. Internal Power-On Reset Timing.
tRST = 40ns minimum
RSTB-pin
tRST
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock Periods
FIGURE 4. RSTB-Pin Reset Timing.
®
10
PCM1800
BB [ BURR-BROWN CORPORATION ]
