Differential Multiplexer Static Accuracy
DISCUSSION OF
PERFORMANCE
DC CHARACTERISTICS
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current mis-
match, load differential impedance mismatch, and common-
mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel ON
resistance (RON), the load impedance, the source impedance,
the load bias current and the multiplexer leakage current.
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
Source resistance loading error;
Multiplexer ON resistance error;
and, dc offset error caused by both load bias current and
multiplexer leakage current.
The effects of these errors can be minimized by following the
general guidelines described in this section, especially for
low-level multiplexing applications. Refer to Figure 2.
Resistive Loading Errors
Load (Output Device) Characteristics
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
•
Use devices with very low bias current. Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.
•
Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resis-
tance and multiplexer ON resistance. As a guideline, load
impedances of 108Ω, or greater, will keep resistive load-
ing errors to 0.002% or less for 1000Ω source imped-
ances. A 106Ω load impedance will increase source
loading error to 0.2% or more.
•
•
The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
•
Use sources with impedances as low as possible. 1000Ω
source resistance will present less than 0.001% loading
error and 10kΩ source resistance will increase source
loading error to 0.01% with a 108 load impedance.
Load impedances, differential and common-mode, should
be 1010Ω or higher.
IBIAS
RS1
RON
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
VM
Measured
Voltage
IL
Source and Multiplexer Resistive Loading Error
RS8
ROFF
VS1
R
S +RON
(RS +RON) =
×100%
R
S +RON +RL
ZL
VS8
where RS = source resistance
RL = load resistance
FIGURE 1. MPC508A DC Accuracy Equivalent Circuit.
RON = multiplexer ON resistance
RS1
RON1A
IBIAS A
Input Offset Voltage
Cd/2
Cd/2
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC508A, the OFFSET voltage at the output is
determined by:
Rd/2
RCM
IL
VS1
ZL
RS1B
RON1B IBIAS B
RCM1
CCM
Rd/2
RS4A
ROFF4A
VOFFSET = (IB + IL) (RON + RS)
ILB
where IB = Bias current of device multiplexer is driving
IL = Multiplexer leakage current
VS8
RS48
ROFF4B
RON = Multiplexer ON resistance
RS = source resistance
RCM4
FIGURE 2. MPC509A DC Accuracy Equivalent Circuit.
MPC508A, MPC509A
5
SBFS019A
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