register. The DVALID output goes LOW when the shift
register contains valid data.
THEORY OF OPERATION
The basic operation of the DDC112 is illustrated in Figure 1.
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol-
lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma converter via a
four input multiplexer. With the DDC112 in the continuous
integration mode, the output of the integrators from one side
of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D con-
version process is controlled by the system clock, CLK.
With a 10MHz system clock, the integrator combined with
the delta-sigma converter accomplishes a single 20-bit con-
version in approximately 220µs. The results from side A and
side B of each signal input are stored in a serial output shift
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on TINT, CLK, and DCLK, it
is possible to daisy chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital
outputs in those cases where a large number of converters
are needed.
AVDD
AGND
VREF
DVDD
DGND
CAP1A
CAP1A
Input 1
DCLK
IN1
Dual
Switched
Integrator
DVALID
DXMIT
DOUT
DIN
CAP1B
CAP1B
∆Σ
Modulator
Digital
Filter
Digital
Input/Output
CAP2A
CAP2A
Input 2
RANGE2
RANGE1
RANGE0
IN2
Control
Dual
Switched
Integrator
CAP2B
CAP2B
TEST
CLK
CONV
FIGURE 1. DDC112 Block Diagram.
IN1, Integrator A
Integrate
Integrate
IN1, Integrator B
IN2, Integrator A
Integrate
Integrate
Integrate
Integrate
Integrate
Integrate
IN1A
IN2A
IN2, Integrator B
Conversion in Progress
IN1B
IN2B
IN1A
IN2A
IN1B
IN2B
DVALID
FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).
®
DDC112
6
BB [ BURR-BROWN CORPORATION ]
