DAC TRANSFER FUNCTION
APPLICATION INFORMATION
THEORY OF OPERATION
The total output current, IOUTFS, of the DAC900 is the
summation of the two complementary output currents:
The architecture of the DAC900 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic D/A converter is an
array of segmented current sources, which are designed to
deliver a full-scale output current of up to 20mA (see
Figure 1). An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/1024)
(2)
(3)
currents to either output summing node, IOUT or IOUT
.
The complementary outputs deliver a differential output
signal, which improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by
a factor of two, compared to single-ended operation.
IOUT = IOUTFS • (1023 - Code/1024)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the refer-
ence current IREF, which is determined by the reference
The segmented architecture results in a significant reduc-
tion of the glitch energy, and improves the dynamic perfor-
mance (SFDR) and DNL. The current outputs maintain a
very high output impedance of greater than 200kΩ.
voltage and the external setting resistor, RSET
.
IOUTFS = 32 • IREF = 32 • VREF/RSET
(4)
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, RSET. The resulting IREF is internally multiplied by
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
of RSET
.
VOUT = IOUT • RLOAD
VOUT = IOUT • RLOAD
(5)
(6)
The DAC900 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches and the
reference circuitry.
+3V to +5V
Digital
+3V to +5V
Analog
0.1µF
Bandwidth
Control
BW
+VA
+VD
DAC900
Full-Scale
Adjust
Resistor
IOUT
IOUT
1:1
VOUT
LSB
Switches
FSA
PMOS
Current
Source
Array
Ref
Control
Amp
Ref
Input REFIN
Segmented
MSB
Switches
50Ω
400pF
RSET
2kΩ
20pF
50Ω
20pF
0.1µF
0.1µF
BYP
INT/EXT
Ref
Buffer
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
+1.24V Ref
10-Bit Data Input
D9...D0
AGND
Analog
CLK
DGND
Clock
Input
Digital
Ground
Ground
NOTE: Supply bypassing not shown.
FIGURE 1. Functional Block Diagram of the DAC900.
®
11
DAC900
BB [ BURR-BROWN CORPORATION ]
