DAISY-CHAINING USING SDO
DAC7731’s in a daisy-chained configuration, as shown in
Figure 7.
Multiple DAC7731’s can be connected to a single serial port
by attaching each of their control inputs in parallel and daisy-
chaining the SDO and SDI I/O's of each device. The SDO
output of the DAC7731 is active when CS is LOW and can
be left unconnected when not required for use in a daisy-
chain configuration.
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause VOUT to
reset to the mid-scale code (8000H) and a LOW value will reset
Once a data transfer cycle begins, new data is shifted into SDI
and data currently residing in the shift register (from previous
cycle, power-up, or reset command) is presented on SDO, MSB
first. One data transfer cycle for each DAC7731 is required to
update all devices in the chain. The first data cycle written into
the chain will arrive at the last DAC7731 on the final cycle of the
data transfer. Upon completion of the required number of data
transfer cycles (one cycle per device), each DAC voltage output
is updated with a rising edge on the LDAC inputs.
Figure 8 shows the required timing to properly update two
VOUT to min-scale (8000H). A change in the state of the RSTSEL
input while RST is LOW will cause a corresponding change in
the reset command selected internally and consequently change
the output value of VOUT of the DAC. Note that a valid reset
signal also resets the input register of the DAC to the value
specified by the state of RSTSEL.
From Host
Controller
To next
DAC7731
DAC7731
DAC7731
VCC
VSS
REFEN
RSTSEL
SCLK
CS
VCC
VSS
REFEN
RSTSEL
SCLK
CS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
24
23
22
21
20
19
18
17
16
15
14
13
REFOUT
REFIN
REFADJ
VREF
REFOUT
REFIN
REFADJ
VREF
3
3
4
4
5
5
ROFFSET
AGND
RFB2
RFB1
SJ
SDO
ROFFSET
AGND
RFB2
RFB1
SJ
SDO
6
6
SDI
SDI
7
7
LDAC
RST
LDAC
RST
8
8
9
9
NC
NC
10
11
12
10
11
12
VOUT
TEST
DGND
VOUT
TEST
DGND
VDD
VDD
First Device in Chain
Second Device in Chain
FIGURE 7. DAC7731 Daisy-Chain Schematic.
Both DAC VOUT's
are updated
LSBs latched
LSBs latched
SCLK
1
2
16
1
2
16
CS
LDAC
First Data Transfer Cycle
A15 A14
SDI
A0
X
B15
A15
B14
A14
B1
A1
B0
A0
Previous cycle word from host
(to DAC7731 B SDI)
SDO
X
X
FIGURE 8. DAC7731 Daisy-Chain Timing for Figure 7.
DAC7731
13
SBAS249
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