DIGITAL INTERFACE
The double buffered architecture is mainly designed so that
each DAC Input Register can be written at any time and then
all DAC output voltages updated simultaneously by pulling
LDAC LOW. It also allows a DAC Input Register to be
written to at any point and the DAC voltage to be synchro-
nously changed via a trigger signal connected to LDAC.
Table I shows the basic control logic for the DAC7724/25.
Note that each internal register is level triggered and not
edge triggered. When the appropriate signal is LOW, the
register becomes transparent. When this signal is returned
HIGH, the digital word currently in the register is latched.
The first set of registers (the Input Registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time. The second set of
registers (the DAC Registers) are all transparent when LDAC
input is pulled LOW.
DIGITAL TIMING
Figure 4 and Table II provide detailed timing for the digital
interface of the DAC7724 and DAC7725.
DIGITAL INPUT CODING
Each DAC can be updated independently by writing to the
appropriate Input Register and then updating the DAC
Register. Alternatively, the entire DAC Register set can be
configured as always transparent by keeping LDAC LOW—
the DAC update will occur when the Input Register is
written.
The DAC7724 and DAC7725 input data is in straight binary
format. The output voltage is given by the following equa-
tion:
V
– VREFL • N
(
)
REFH
VOUT = VREFL
+
4096
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) errors.
STATE OF
SELECTED
INPUT
SELECTED
INPUT
STATE OF
ALL DAC
A1
A0
R/W
CS
RESET
LDAC
REGISTER
REGISTER
REGISTERS
L(1)
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H(2)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
A
B
C
D
A
B
C
D
A
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Readback
Readback
Readback
Readback
(All Latched)
(All Latched)
Reset(4)
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Reset(4)
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
B
C
D
H
H
X(3)
X
NONE
NONE
ALL
H
X
X
NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7724 resets to 800H, DAC7725 resets to 000H. When RESET rises, all registers
that are in their latched state retain the reset value.
TABLE I. DAC7724 and DAC7725 Control Logic Truth Table.
®
14
DAC7724, 7725
BB [ BURR-BROWN CORPORATION ]
