DAC7634
www.ti.com
SBAS134A–JULY 2004–REVISED AUGUST 2004
DIGITAL INTERFACE
The DAC code, quick load control, and address are
provided via a 24-bit serial interface (see Figure 15).
The first two bits select the input register that is
updated when LOAD goes LOW. The third bit is a
Quick Load bit such that if HIGH, the code in the shift
register is loaded into ALL DAC's input register when
LOAD signal goes LOW. If the Quick Load bit is
LOW, the content of shift register is loaded only to
the DAC input register that is addressed. The Quick
Load bit is followed by five unused bits. The last
sixteen bits (MSB first) are the DAC code.
Table 1 shows the basic control logic for the
DAC7634. The interface consists of a signal data
clock (CLK) input, serial data (SDI), DAC input
register load control signal (LOAD), and DAC register
load control signal (LDAC). In addition, a chip select
(CS) input is available to enable serial communication
when there are multiple serial devices. An asynchro-
nous reset (RST) input, by the rising edge, is pro-
vided to simplify start-up conditions, periodic resets,
or emergency resets to a known state, depending on
the status of the reset select (RSTSEL) signal.
SERIAL DATA INPUT
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
QUICK
LOAD
A1
A0
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 1. DAC7634 Logic Truth Table(1)
INPUT
REGISTER
DAC
REGISTER
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
MODE
DAC
L
L
L
H
L
L
L
H
H
H
H
H
H
↑
X
X
X
X
X
X
L
X
X
X
X
↑
L
L
Write
Write
Hold
Hold
Write Input
Write Input
Write Input
Write Input
Update
A
B
H
H
X
X
X
X
L
L
Write
Hold
C
H
X
X
X
X
L
L
Write
Hold
D
H
H
X
X
H
H
X
X
Hold
Write
All
All
All
All
H
X
X
Hold
Hold
Hold
Reset to Zero
Reset to Midscale
Reset to Zero
Reset to Zero
↑
H
Reset to Midscale
Reset to Midscale
(1) If the DAC7634 is the only device on the serial bus, the CS pin can be connected to DGND permanently, which enables the shift register
all the time. In this case, only the CLK operates the serial shift register and all other functions listed in Table 1 should be followed as
shown. The DAC updates on the rising edge of LDAC.
The internal DAC register is edge-triggered and not
Note that CS and CLK are combined with an OR
level-triggered. When the LDAC signal is transitioned
gate, which controls the serial-to-parallel shift regis-
from LOW to HIGH, the digital word currently in the
ter. These two inputs are completely interchangeable.
DAC input register is latched. The first set of registers
In addition, care must be taken with the state of CLK
(the DAC input registers) are level-triggered via the
when CS rises at the end of a serial transfer. If CLK
LOAD signal. This double-buffered architecture has
is LOW when CS rises, the OR gate provides a rising
been designed so that new data can be entered for
edge to the shift register, shifting the internal data
each DAC without disturbing the analog outputs.
one additional bit. The result will be incorrect data
When the new data has been entered into the device,
and possible selection of the wrong input register(s).
all of the DAC outputs can be updated simultaneously
If both CS and CLK are used, CS should rise only
by the rising edge of LDAC. Additionally, it allows the
when CLK is HIGH. If not, then either CS or CLK can
DAC input registers to be written to at any point, then
be used to operate the shift register. See Table 2 for
the DAC output voltages can be synchronously
more information.
changed via a trigger signal (LDAC).
22
BB [ BURR-BROWN CORPORATION ]
