TIMING DIAGRAMS
(MSB)
D11
(LSB)
D0
SDI
CLK
CS
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
tCSS
tCSH
tLD1
tLD2
LOADDACS
tDS
tDH
SDI
tCL
tCH
CLK
tLDW
LOADDACS
tS
FS
±1 LSB
Error Band
VOUT
ZS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
TA = –40°C to +85°C and VDD = +5V.
SERIAL SHIFT
A0 CLK CS LOADDACS REGISTER
DAC
DAC
A1
REGISTER A REGISTER B
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
X
X
L
X
X
X
X
↑
X
H
L
H(1)
H
H
L
No Change
Shifts One Bit
No Change
No Change
No Change
No Change
No Change
tCH
tCL
tLDW
tDS
Clock Width HIGH
Clock Width LOW
Load Pulse Width
Data Setup
30
30
20
15
15
15
10
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Loads Serial
Data Word
Loads Serial
Data Word
H
H
L
X
X
H
H
L
L
No Change
No Change
Loads Serial
Data Word
No Change
tDH
Data Hold
H
No Change
Loads Serial
Data Word
tLD1
tLD2
tCSS
tCSH
Load Setup
Load Hold
↑ Positive Logic Transition; X = Don’t Care.
Select
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
Deselect
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
DATA INPUT TABLE
B0
A1
B1 B2 B3
B4 B5 B6
B7 B8 B9 B10 B11 B12 B13
D6 D5 D4 D3 D2 D1 D0
A0 D11 D10 D9 D8 D7
®
5
DAC7612
BB [ BURR-BROWN CORPORATION ]
