TIMING DIAGRAMS
(MSB)
SDI
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)
D0
CLK
t
CSS
CS
t
LD1
LD
t
LD2
t
CSH
t
DS
SDI
t
CL
CLK
t
DH
t
CH
t
LDW
LD
t
CLRW
CLR
FS
V
OUT
ZS
t
S
±1
LSB
Error Band
t
S
LOGIC TRUTH TABLE
CS
(1)
H
L
L
L
↑
H
(2)
H
(2)
H
H
CLK
(1)
X
L
H
↑
L
X
X
X
X
CLR
H
H
H
H
H
H
H
L
↑
LD
H
H
H
H
H
↓
L
(3)
X
H
SERIAL SHIFT
REGISTER
No Change
No Change
No Change
Advanced One Bit
Advanced One Bit
No Change
No Change
No Change
No Change
DAC REGISTER
No Change
No Change
No Change
No Change
No Change
Changes to Value of
Serial Shift Register
Transparent
Loaded with 000
H
Latched with 000
H
TIMING SPECIFICATIONS
T
A
= –40°C to +85°C and V
DD
= +5V.
SYMBOL
t
CH
t
CL
t
LDW
t
DS
t
DH
t
CLRW
t
LD1
t
LD2
t
CSS
t
CSH
DESCRIPTION
Clock Width HIGH
Clock Width LOW
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
Select
Deselect
MIN TYP MAX UNITS
30
30
20
15
15
30
15
10
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
↑
Positive Logic Transition;
↓
Negative Logic Transition; X = Don’t Care.
NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggested
in order to avoid to “false clock” from advancing the shift register and changing
the DAC voltage. (3) If data is clocked into the serial register while LD is LOW,
the DAC output voltage will change, reflecting the current value of the serial
shift register.
NOTE: All input control signals are specified with t
R
= t
F
= 5ns (10% to 90%
of +5V) and timed from a voltage level of 1.6V. These parameters are
guaranteed by design and are not subject to production testing.
®
5
DAC7611
BURR-BROWN [ BURR-BROWN CORPORATION ]
