4
2
Data
Data Latch
Update
SDI
A0
3
A1
DAC714
DAC714
DAC714
1
CLK
CLR
CLK
+5V
+5V
+5V
16
5
5
5
SDO
SDO
SDO
4
2
SDI
A0
3
A1
1
CLK
CLR
16
4
2
SDI
A0
3
A1
1
CLK
CLR
16
To other DACs
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
DAC3
DAC2
DAC1
Clock(1)
Data
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
F
E
D
C
B
A
9
8
7
6
5
4
3
2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0
Data Latch
Update
NOTE: (1) Maximum Clock Frequency is 5.26MHz.
FIGURE 8b. Timing Diagram For Figure 8a.
®
12
DAC714