www.ti.com
SLAS386A – JULY 2005 – REVISED JUNE 2006
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V
PARAMETER
t
(CONV)
t
(ACQ)
t
(HOLD)
t
pd1
t
pd2
t
pd3
t
w1
t
su1
t
w2
t
w3
t
w4
t
h1
t
d1
t
su2
t
w5
t
en
t
d2
t
d3
t
w6
t
w7
t
h2
t
pd4
t
d4
t
su3
t
h3
t
dis
t
d5
t
d6
t
d7
t
su5
Conversion time
Acquisition time
Sample capacitor hold time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
Delay time, CS low to RD low
Setup time, RD high to CS high
Pulse duration, RD low
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
Pulse duration, RD high
Pulse duration, CS high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
Delay time, BYTE edge to BUS18/16 edge skew
Setup time, BYTE or BUS18/16 transition to RD falling edge
Hold time, BYTE or BUS18/16 transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16
transition setup time, from BUS18/16 to next BUS18/16.
50
50
50
60
550
5
10
20
20
50
0
0
10
10
20
0
20
40
0
0
50
20
t
(ACQ)
min
650
40
20
20
10
320
25
40
15
15
(1) (2) (3)
MIN
TYP
MAX
650
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
su(ABORT)
Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
(1)
(2)
(3)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See timing diagrams.
All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
6
BURR-BROWN [ BURR-BROWN CORPORATION ]
