SPECIFICATIONS
At T
A
= full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted.
ADS823E
MIN
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range
(2)
f = 1MHz
f = 10MHz
Two-Tone Intermodulation Distortion
(4)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits
(5)
, f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
(5)
Full-Scale Step Acquisition Time
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current
(6)
(V
IN
= 5V)
Low Level Input Current (V
IN
= 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50µA to 1.6mA)
High Output Voltage, (I
OH
= 50µA to 0.5mA)
Low Output Voltage, (I
OL
= 50µA to 1.6mA)
High Output Voltage, (I
OH
= 50µA to 0.5mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
Ambient Air
2Vp-p
1Vp-p
2Vp-p
1.5
2
2.5
2
1
1.25 || 5
300
10k
5
60M
T
T
3
T
T
T
T
T
TYP
10 Guaranteed
–40 to +85
3.5
3
T
T
T
T
MAX
MIN
ADS826E
(1)
TYP
10 Guaranteed
–40 to +85
T
T
MAX
UNITS
Bits
°C
V
V
V
V
µA
MΩ || pF
MHz
Samples/s
Clk Cyc
–3dBFS Input
±0.25
±0.25
Guaranteed
±0.5
74
74
64
Referred to Full-Scale Sinewave
57
Referred to Full-Scale Sinewave
56
Input Grounded
59
59
9.5
0.2
3
1.2
2
5
60
60
±1.0
±2.0
T
T
Guaranteed
T
73
73
T
59
59
58
58
T
T
T
T
T
T
T
LSB
LSB
LSBs
dBFS
(3)
dBFS
dBc
dB
dB
dB
dB
Bits
LSBs rms
ns
ps rms
ns
ns
T
67
65
56
55
Start Conversion
CMOS-Compatible
Rising Edge of Convert Clock
+100
+10
+3.5
+1.0
5
CMOS
Straight Offset Binary
+0.1
+4.9
+0.1
+2.8
2
40
2
10
5
±1.0
16
±1.5
66
±1.0
23
70
±10
±10
3.5
1.5
1.6
±3.0
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
T
T
+2.0
+0.8
T
CMOS
Straight Offset Binary
T
T
T
T
T
T
T
T
T
T
T
±0.29
T
T
T
T
T
T
T
T
T
T
T
µA
µA
V
V
pF
VDRV = 5V
VDRV = 3V
OE = H to L
OE = L to H
V
V
V
V
ns
ns
pF
% FS
ppm/°C
% FS
% FS
ppm/°C
% FS
ppm/°C
dB
mV
mV
V
V
kΩ
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (referred to –FS)
At 25°C
Zero Error Drift (referred to –FS)
Midscale Offset Error
At 25°C
Gain Error
(7)
At 25°C
Gain Error Drift
(7)
Gain Error
(8)
At 25°C
Gain Error Drift
(8)
Power Supply Rejection of Gain
∆
V
S
=
±5%
REFT Tolerance
Deviation From Ideal 3.5V
REFB Tolerance
Deviation From Ideal 1.5V
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
REFT to REFB
2.5
1.5
T
±25
±25
V
S
– 1.25
REFT – 0.8
T
T
50
REFB + 0.8
1.25
T
T
T
T
T
T
®
ADS823, ADS826
2
BURR-BROWN [ BURR-BROWN CORPORATION ]
