PIN ASSIGNMENTS
PIN #
NAME
I/O
DESCRIPTION
1
2
LN 0
LN 1
Analog Input
Analog Input
MUX Input Line 0
MUX Input Line 1
3
LN 2
Analog Input
MUX Input Line 2
4
LN 3
Analog Input
MUX Input Line 3
5
LN 4
Analog Input
MUX Input Line 4
6
LN 5
Analog Input
MUX Input Line 5
7
LN 6
Analog Input
MUX Input Line 6
8
LN 7
Analog Input
MUX Input Line 7
9
RESET
RISE/FALL
I/O 0
Digital Input
Master Reset zero’s all registers.
Sets the active edge for SCLK. “0” sets SCLK active on falling edge. “1” sets SCLK active on rising edge.
Digital Input or Output signal
10
11
12
13
14
15
16
17
18
19
Digital Input
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
No Connection
Digital Input
I/O 1
Digital Input or Output signal
I/O 2
Digital Input or Output signal
I/O 3
Digital Input or Output signal
NC
Do not connect to this pin.
CONVERT
BUSY
OSC ENABLE
CCLK
“0” to “1” transition starts a conversion cycle.
“1” indicates converter is busy
Digital Output
Digital Input
“0” sets CCLK as input, “1” sets CCLK as output and turns oscillator on.
Digital Input/Output
If OSC ENABLE = “1” then Internal Oscillator is output to this pin. If OSC ENABLE = “0” then this is
the input pin for an external conversion clock.
20
21
22
23
SCLK
DIN
Digital Input
Digital Input
Digital Output
Digital Input
Serial Data Input/Output Transfer Clock. Active edge set by the RISE/FALL pin. If RISE/FALL is low,
SCLK is active on the falling edge.
Serial Data Input. In the 3-wire mode, this pin is used for serial data input. In the 2-wire mode serial
data, output appears on this pin as well as the DOUT pin.
DOUT
CS
Serial Data Output. This pin is driven when CS is low and is high impedance when CS is high. This
pin behaves the same in both 3-wire and 2-wire modes.
Chip Select. When CS is low the serial interface is enabled. When CS is high the serial interface is
disabled, the DOUT pin is high impedance, and the DIN pin is an input. The CS pin only effects the
operation of the serial interface. It does not directly enable/disable the operation of the signal
conversion process.
24
25
26
27
28
VDD
GND
Power
Power
Power Supply Voltage, +2.7V to +5.5V.
Power Supply Ground.
VREF
Analog Output
Analog Input
Analog Output/Input
2.048V/2.5V On-Chip Voltage Reference
Input to Reference Buffer Amplifier
BUFIN
BUFOUT/REFIN
Output from Reference Buffer Amplifier and Reference Input to ADC.
®
5
ADS7870
BB [ BURR-BROWN CORPORATION ]
