TRANSITION NOISE
R1
Figure 5 shows a histogram plot for the ADS7864 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7864.
4kΩ
+IN
–IN
OPA340
20kΩ
Bipolar Input
ADS7864
R2
BIPOLAR INPUTS
REFOUT (pin 33)
2.5V
The differential inputs of the ADS7864 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7864 can be configured to except bipolar
inputs. The conventional ±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7864 using the resistor
values shown in Figure 7.
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
THEORY OF OPERATION
The ADS7864 contains two 12-bit A/D converters that operate
simultaneously. The three hold signals (HOLDA, HOLDB,
HOLDC) select the input MUX and initiate the conversion. A
simultaneous hold on all six channels can occur with all three
hold signals strobed together. The converted values are saved
in 6 registers. For each read operation the ADS7864 outputs
16 bits of information (12 Data, 3 Channel Address and Data
Valid). The Address/Mode signals (A0, A1, A2) select how
the data is read from the ADS7864. These Address/Mode
signals can define a selection of a single channel, a cycle mode
that cycles through all channels or a FIFO mode that se-
quences the data determined by the order of the Hold signals.
The FIFO mode will allow the 6 registers to be used by a
single channel pair and therefore three locations for CH X0
and three locations for CH X1 can be acquired before they are
read from the part.
TIMING AND CONTROL
The ADS7864 uses an external clock (CLOCK, pin 22)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2µs maximum throughput time.
8000
7000
6000
5000
4000
3000
2000
1000
0
EXPLANATION OF CLOCK, RESET
AND BUSY PINS
2044
2045
2046
2047
2048
Code (decimal)
CLOCK—An external clock has to be provided for the
ADS7864. The maximum clock frequency is 8MHz. The
minimum clock cycle is 125ns (Figure 8, t5 ), and the clock
has to remain HIGH (Figure 8, t6) or LOW (Figure 8, t7) for
at least 40ns.
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
1.4V
RESET—Bringing reset LOW will reset the ADS7864. It
will clear all the output registers, stop any actual conversions
and will close the sampling switches. Reset has to stay LOW
for at least 20ns (Figure 8, t8). The reset should be back
HIGH for at least 20ns (Figure 8, t9), before starting the next
conversion (negative hold edge).
3kΩ
DATA
Test Point
100pF
CLOAD
VOH
DATA
BUSY—Busy goes LOW when the internal A/D converters
start a new conversion. It stays LOW as long as the conver-
sion is in progress (Figure 9, 13 clock-cycles, t10) and rises
again, after the data is latched to the output register. With
busy going high, the new data can be read. It takes at least
16 clock cycles (Figure 9, t11) to complete conversion.
VOL
tR
tF
Voltage Waveforms for DATA Rise and Fall Times tR, and tF.
FIGURE 6. Test Circuits for Timing Specifications.
®
ADS7864
10
BB [ BURR-BROWN CORPORATION ]
