15 Clocks-per-Conversion
8-Bit Conversion
Figure 12 provides the fastest way to clock the ADS7846.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method can be used with field pro-
grammable gate arrays (FPGAs) or application specific inte-
grated circuits (ASICs). Note that this effectively increases
the maximum conversion rate of the converter beyond the
values given in the specification tables, which assume 16
clock cycles per conversion.
The ADS7846 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. Not only does this shorten
each conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the ADS7846 is not as
critical—settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock rate
and fewer clock cycles combine to provide a 2x increase in
conversion rate.
Data Format
The ADS7846 output data is in Straight Binary format as
shown in Figure 13. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
POWER DISSIPATION
There are two major power modes for the ADS7846: full power
(PD0 = 1B) and auto power-down (PD0 = 0B). When operating
at full speed and 16 clocks-per-conversion (see Figure 10), the
ADS7846 spends most of the time acquiring or converting.
There is little time for auto power-down, assuming that this
mode is active. Therefore, the difference between full-power
mode and auto power-down is negligible. If the conversion
rate is decreased by slowing the frequency of the DCLK input,
the two modes remain approximately equal. However, if the
DCLK frequency is kept at the maximum rate during a conver-
sion but conversions are done less often, the difference
between the two modes is dramatic.
(1)
FS = Full-Scale Voltage = VREF
1LSB = VREF(1)/4096
1LSB
11...111
11...110
11...101
00...010
00...001
00...000
0V
FS – 1LSB
Input Voltage(2) (V)
NOTES: (1) Reference voltage at converter: +REF – (–REF), see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN), see Figure 2.
FIGURE 13. Ideal Input Voltages and Output Codes.
CS
Power Down
DCLK
1
15
1
15
1
SGL/
DIF
SGL/
DIF
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
Tri-State
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
FIGURE 12. Maximum Conversion Rate, 15 Clocks-per-Conversion.
ADS7846
SBAS125H
15
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