SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
PD1
0
PD0
0
Description
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.5
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tDO
tDV
200
200
200
tTR
0
1
1
1
0
1
Reserved for future use.
Reserved for future use.
tCSS
tCSH
tCH
100
0
No power-down between conversions, device al-
ways powered.
200
200
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
TABLE V. Power-Down Selection.
tBDV
tBTR
Digital Timing
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7844.
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
15-Clocks per Conversion
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
900
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 6 provides the fastest way to clock the ADS7844.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
tDH
10
tDO
tDV
100
70
tTR
70
tCSS
tCSH
tCH
50
0
150
150
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
100
70
tBDV
tBTR
70
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
1
15
1
15
1
SGL/
SGL/
DIN
BUSY
DOUT
S
A2 A1 A0
PD1 PD0
S
A2 A1 A0
PD1 PD0
S
A2 A1 A0
DIF
DIF
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
®
ADS7844
12
BB [ BURR-BROWN CORPORATION ]
