microcontrollers form various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(master in slave out).
FS = Full-Scale Voltage = VREF
1 LSB = FS/4096
1 LSB
11...111
11...110
11...101
Note the time tDRP shown in Figure 9. This represents the
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor loses charge over time, there is a requirement
that time tDRP be met as well as the maximum clock period
(tCKP).
00...010
00...001
00...000
0V
2.499V(1)
LAYOUT
Input Voltage(2) (V)
For optimum performance, care should be taken with the
physical layout of the ADS7834 circuitry. This is particu-
larly true if the CLK input is approaching the maximum
input rate.
NOTES: (1) For external reference, value is VREF – 1 LSB. (2) Voltage
at converter input: +IN – (–IN).
FIGURE 7. Ideal Input Voltages and Output Codes.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the CLK
input.
DSP INTERFACING
Figure 8 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
buffered serial port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 9 shows the timing diagram for a typical serial
peripheral interface (SPI) or queued serial peripheral inter-
face (QSPI). Such interfaces are found on a number of
CONV
15
16
1
2
3
12
13
14
15
16
1
2
3
4
CLK
D11
(MSB)
D0
(LSB)
D11
(MSB)
DATA
D10
D1
D10
D9
FIGURE 8. Typical DSP Interface Timing.
tDRP
tACQ
CONV
1
2
3
4
13
14
15
16
1
2
3
CLK
D11
(MSB)
D0
(LSB)
D11
(MSB)
DATA
D10
D1
FIGURE 9. Typical SPI/QSPI Interface Timing.
®
ADS7834
12
BB [ BURR-BROWN CORPORATION ]
